Drain-extended metal oxide semiconductor (DEMOS) devices are extensively used in analog technologies as interfaces between low-voltage processing circuitry and high-voltage off-chip devices. The use of DEMOS devices as interface elements implies that they are often in the critical path for electro static discharge (ESD) events. DEMOS devices are well known to have poor drain-to-source ESD current handling capability due to kirk-effect induced voltage snapback. The poor ESD current handling capabilities of the DEMOS devices and their locations in the critical paths for ESD events results in the DEMOS devices having significant failure rates.
The current ESD protection strategy for DEMOS devices involves either using parallel ESD clamps or relying on self protection. Parallel ESD clamps provide a route for the current generated during an ESD event to bypass terminals on the DEMOS devices, such as the drain/source path. The addition of parallel ESD clamps often requires significant area overhead on the integrated circuit on which the DEMOS devices are fabricated and may impose limitations on the maximum slew-rate of output signals generated by the DEMOS devices. In some situations, unanticipated failures may occur as a result of race conditions between the protected DEMOS devices and the ESD clamps.
Self protection relies on keeping the DEMOS devices turned on during ESD events, which clamps the voltage on the device terminals during ESD events. However, the gate voltages of the DEMOS devices cannot be guaranteed to stay high during ESD events, mainly due to parasitic paths and circuit loading. Therefore, self protection is achieved only by relying on the current handling capability of the device in breakdown mode, referred to as IT1, with zero gate to source voltage (VGS). Relying on self protection in breakdown mode requires the protected device being physically large enough to pass the IT1 current. Some devices require a total DEMOS device width greater than 10,000 um for 2 kV in the human body model (HBM), and require the breakdown current IT1 to scale with the DEMOS device width and the number of gate fingers. The large sizes of the DEMOS devices increase the costs of the devices and present other problems.